Experimental Digital Delay line
The  following is  an experimental  Digital audio  delay line.  The circuit  is
pretty much as was published in 'electronics  and wireless  world' in  December
1986. Except that I've also designed an LFO modulated clock source  so that  it
can do a variety of effects. Because of the simplicity of the  over all  logic,
it's delay range is somewhat limited. At some  point, the  pulse delay  circuit
around IC 2b will be too slow for the incoming clock pulse but  usually not  to
the point where it isn't still useful.

The delay scheme uses Sigma-Delta. That is to  say that  it differentiates  the
rate of change of an incoming wave form and stores the value in a single bit of
memory. It then integrates this value back across a capacitor at the output and
reconstitutes the wave form. Because of the nature of the conversion technique,
there is no need for an anti-aliasing filter. Or at least  that is  to say  the
filtering is inherent in  the process.  The memory  chip simply  stores a  high
speed stream of bits. If the wave form was rising, the bits would always be  1.
If the waveform was falling the bits would always be zero. If the waveform  was
at a steady DC state then the bit's would be a constant stream of ones followed
by zeros. This is because the conversion  technique simply  compares the  input
wave form with an instantaneous value stored temporarily across a capacitor. If
the input is higher  than the  capacitor it  simply remembers  that state.  The
capacitor voltage is then updated and the process  repeated. It's  all done  so
fast that an audio waveform of reasonable quality can be  encoded. Infact  it's
so  good  I  can't tell  the difference  until the  clock is  really slow.  The
equivalent bit resolution is proportional to the clock rate although the  exact
formula I'm not sure.

The D-A converter is simply the opposite. The output is the stored  value of  a
capacitor buffered by a high impedance op-amp. If the bit is a one, the voltage
on the capacitor goes up. If the bit  is a  zero the  voltage on  the cap  goes
down. If it  is a  constant stream  of alternate  ones and  zeros, the  voltage

This is  almost identical  to the  D-A conversion  scheme used  in most  modern
digital  audio  systems   though  these   integrated  systems   are  far   more
sophisticated. For  example, If  the pulse  delay and  other logic  were to  be
replaced with true timing generation, this system would be able to clock at any
speed. From DC to as fast as the RAM would enable.

Of course more RAM can be added for longer delays or less  RAM clocked  through
in order to have very short delays for effects such as flanging and  chorusing.
However it's main use  is to  demonstrate the  Sigma-delta conversion  process.
Another  use  I  found for  this technology  was Audio  transmission over  long
distances in digital form. It's not as snazzy as AES-EBU but it can be done  on
the cheap and doesn't need a bucked load of microprocessors to  look after  it.
Replace the RAM with suitable drivers and  send the  clock out  along with  it.
There's so much room for experimentation here that I've not even begun to  mess
with this concept in this form.

Thanks  very much  to the  persons who's  names allude  me who  thought up  the
original circuit. Appropriate accreditation will be included in this text  when
I find the magazine out from under a pile in my library. The  system works  and
is worth building but I've mainly included it here  out of  interest for  those
whishing to experiment with the concepts. Have fun.

digital delay circuit gif View or Download
Schematic in
GIF file format